The invention relates to a method for modifying a representation of a digital circuit in order to allow a scan test, the digital circuit comprising one or more combinational subcircuits and one or more memory elements, the method comprising: a selection step for selecting from the memory elements a number of the memory elements to be made scannable, a replacement step for replacing the selected memory elements by respective scannable memory elements, and a connection step for connecting the scannable memory elements into one or more scan chains.
When testing a circuit, it is determined whether the circuit contains a logical fault resulting from a manufacturing defect. A combinational circuit, this is a circuit that includes no memory elements like flip flops, is tested by applying a number of test patterns to the inputs of the circuit and comparing the observed responses on the outputs of the circuit with expected responses. The test patterns are selected in such a way that a possible logical fault in the circuit will for at least one test pattern result in a response deviating from its expected response. The test patterns and corresponding responses can be generated for a given circuit by a so-called Automatic Test Pattern Generator. If the circuit to be tested includes memory elements it becomes difficult to generate a set of test patterns that covers all possible faults. This is because a response on the outputs of such a circuit does not only depend on the currently applied test pattern on the inputs but also on the current contents of the memory elements. Test patterns for such a circuit are generated by a so-called Sequential Test Pattern Generator. It is generally known that such a generator requires a large computational effort. This problem is solved in the scan test approach by giving the memory elements in addition to their normal functional mode a scan mode. In the scan mode, these scannable memory elements form one or more scan chains connecting to a scan input and scan output of the circuit through which patterns can be shifted into and out of the chain. The scannable memory element can be seen as a pseudo input for the circuit since a desired input value can be applied to the circuit through the memory element. In a similar way, the scannable memory element can be seen as a pseudo output. If for a given circuit all memory elements are substituted by respective scannable memory elements, the resulting circuit can for test purposes be regarded as a combinational circuit. Test patterns covering all logical faults can then be generated for the circuit to be applied to the original, primary inputs and to the scannable memory elements in the same way as for a combinational circuit. A scan test of a circuit includes the following steps:
setting the memory elements into the scan mode, shifting a pattern through the scan chain in such a way that the relevant memory elements receive desired values, PA1 setting the memory elements into the functional mode, PA1 while applying selected values on the primary inputs executing one step in the circuit, forming a response based on the values on the primary inputs and in the memory elements, and observing the responses on the primary outputs, PA1 setting the memory elements into the scan mode, PA1 shifting a pattern out of the scan chain to observe the response formed in the memory elements. PA1 a scannable memory element requires more silicon area on the integrated circuit than an ordinary memory element, PA1 a scannable memory element requires additional wires for connection to other scannable elements and for scan control to set the scannable memory element into the scan mode, PA1 a scannable memory element has a degraded performance because of the added scan functionality, and PA1 the scan chain containing the scannable memory elements is in general quite long, even when multiple scan chains are used, and this causes a large number of test cycles for shifting patterns into and out of the scan chain.
The substitution of the memory elements of a circuit by respective scannable memory elements brings the advantage that the resulting circuit is a combinational circuit and that test patterns for it can be generated by a Combinational Automatic Test Pattern Generator. However scan test also involves a number of costs:
To reduce these costs, scan test methods have been developed in which not all memory elements of the circuit are substituted by scannable memory elements, while maintaining the advantage that it is easier to generate test patterns for the modified circuit than for the original circuit. These methods are called incomplete scan or partial scan. Such a partial scan method is described in the article "The BALLAST Methodology for Structured Partial Scan Design", Rajesh Gupta, Rajiv Gupta and Melvin A. Breuer, IEEE Transactions on Computers, Vol. 39, No. 4, pp. 538-544, April 1990. In this known method, the selection as to what memory elements should be made scannable is carried out in such a way that the test patterns for the modified circuit can be generated with a Combinational Automatic Pattern Generator, while the original sequential circuit would have required a Sequential Automatic Test Pattern Generator. This is realised by selecting memory elements to be made scannable in such a way that every directed cycle of the circuit contains at least one scannable memory element. Furthermore, in this known method the memory elements that are not made scannable together with the combinational subcircuits form balanced structures for which test patterns can be generated in a relatively easy way. In the known method, test patterns are generated with a Combinational Automatic Test Pattern Generator with a fault coverage that is the same as the fault coverage that would be achieved by an ideal Sequential Automatic Test Pattern Generator for the original, unmodified circuit.